As microelectronic devices have been continuously provided with a larger integration scale, planarization processes used for manufacturing such microelectronic devices have become more and more important. As a part of attempts to obtain very large scale integrated microelectronic devices, multiple interconnection technique and multilayer stacking technique have generally been used for semiconductor wafers. However, non-planarization occurring after carrying out one of the above techniques causes many problems. Therefore, planarization processes are applied to various steps in a microelectronic device manufacturing process, so as to minimize irregularity on wafer surfaces.
One of these planarization techniques is CMP (chemical mechanical polishing). During the process of CMP, a wafer surface is pressed against a polishing pad that rotates relative to the surface, and a chemical reagent known as CMP slurry is introduced into the polishing pad during the polishing process. Such CMP technique accomplishes planarization of a wafer surface by way of chemical and physical actions. In other words, CMP technique accomplishes planarization of a wafer surface by pressing the wafer surface against the polishing pad that rotates relative to the surface, and by supplying a chemically active slurry to the wafer surface having a pattern at the same time.
One embodiment, to which CMP technique is applied, is STI (shallow trench isolation). The STI process has been recently developed so as to solve the problem occurring in the conventional LOCOS (local oxidation of silicon) processes and to make electric insulation between chips. This is because the conventional LOCOS processes cause the problem of a so-called Bird's Beak phenomenon, while minimum line width standard becomes more strict to a degree of 0.13 μm or less. In the STI technique, relatively shallow trenches are formed, and such trenches are used in forming field regions for separating active regions on wafer surfaces.
As shown in FIG. 1, in the STI process, a pad silicon oxide (SiO2) layer 101 and a silicon nitride (SiN) layer 102 are formed successively on a semiconductor wafer. Next, a photoresist pattern is formed on the SiN layer 102. Then, the SiN layer 102, the pad silicon oxide layer 101 and the semiconductor wafer 100 are partially etched by using the photoresist pattern as a mask, so that a plurality of trenches 103 is formed.
Further, in order to form field regions, an insulating silicon oxide layer 104 is deposited by way of LPCVD (low pressure chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition) or HDPCVD (high density plasma chemical vapor deposition) technique, so that the trenches 103 are filled with the layer 104 and the surface of the SiN layer 102 is covered with the layer 104.
Subsequently, the insulating silicon oxide layer 104 is polished until the SiN layer 102 is exposed. Additionally, the SiN layer 102 placed between two adjacent active regions, as well as the pad silicon oxide layer 101 is removed by etching. Finally, a gate silicon oxide layer 105 is formed on the surface of the semiconductor wafer.
Herein, during the progress of the CMP process for removing the insulating silicon oxide layer 104, the insulating silicon oxide layer 104 and the SiN layer 102 show different removal rates due to their different chemical and physical properties.
The ratio of the removal rate of the insulating silicon oxide layer to that of the silicon nitride layer is referred to as the selectivity of CMP slurry.
As the selectivity of CMP slurry decreases, the amount of the SiN layer removed by the slurry increases. It is preferable that the SiN layer is not removed. In other words, preferably the selectivity of the insulating silicon oxide layer to the SiN layer is more than 30:1. However, conventional CMP slurry has a low polishing selectivity of the insulating silicon oxide layer to the SiN layer, which is about 4:1. Hence, the SiN layer is polished to a degree exceeding the acceptable range in a practical CMP process.
As a result, the SiN layer pattern may be removed non-uniformly depending on locations in a wafer during a CMP process. Therefore, the SiN layer has a variable thickness over the whole wafer. Particularly, this is a serious problem in the case of a semiconductor wafer that has a highly dense pattern simultaneously with a sparse pattern.
Due to the above-mentioned problem, a final structure having field regions has a level difference between active regions and field regions, resulting in reduction of the margin of subsequent steps for manufacturing a semiconductor device, and degradation of the quality of a transistor and a device. Briefly, conventional CMP processes are problematic in that a SiN layer pattern with a uniform thickness cannot be obtained even after removing the oxide layer via a CMP process.
Therefore, many attempts have been made recently to develop a slurry composition that can control the removal rate of the insulating silicon oxide layer to be higher than the polishing rate of the SiN layer. For example, such slurry composition is disclosed in U.S. Pat. No. 5,614,444; Japanese Laid-Open Patent Nos. 1998-106988, 1998-154672, 1998-270401, 2001-37951, 2001-35820 and 2001-319900; and Korean Laid-Open Patent Nos. 2001-108048, 2002-0015697, 2003-0039999, 2004-0057653, 2004-0013299 and 2003-0039999.
However, such techniques according to the prior art are problematic in that their application ranges are too broad and are not clearly defined, and merely provide basic information about polishing rates and selectivity ratios. Therefore, such techniques are not practically applicable.
In addition to the above, domestic semiconductor and slurry fabricating companies have developed an additive for increasing the polishing selectivity of cerium oxide slurry, the additive comprising a linear polymer alone or in combination with a low-molecular weight material. Such additives are disclosed in Korean Laid-Open Patent Nos. 2003-0039999, 2004-0098671, 2004-0095118 and 2005-0004051.
However, there is no disclosure about CMP slurry containing a graft type polyelectrolyte in the above techniques according to the prior art. Particularly, there is no disclosure about a fluorine-based compound for use in reducing generation of scratch or improving a polishing rate.